Method of forming an insulating layer in a trench isolation type semiconductor device

ABSTRACT

A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH 2 NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming a device isolationlayer in a semiconductor device and, more particularly, to a method offorming a trench-type device isolation layer using an SOG (spin onglass) layer.

2. Description of Related Art

As the integration level of semiconductor devices increases, shallowtrench isolation (STI) type device isolation layers are increasinglybeing used. In a device isolation method employing STI, an oxide layerfills a trench that is formed by etching a semiconductor substrate. TheSTI technique is used to avoid a “bird's beak” phenomenon resulting froma conventional technique such as local oxidation of silicon (LOCOS).

However, an aspect ratio rises rapidly with the trend toward large scaleintegration circuits (LSI). In other words, a width of a trench to befilled with a device isolation layer decreases while a depth thereof ismaintained at the same level. This arrangement makes it necessary tofill up a trench with a void-free or seam-free silicon oxide layer.

Therefore, various approaches have been made for achieving an oxidelayer that is capable of filling up a trench having a high aspect ratio.One of the approaches is to form an oxide layer having excellentgap-fill characteristics using TEOS (tetra-ethyl-ortho-silicate), USG(undoped silicate glass) or HDP (high density plasma). However, if anaspect ratio is 5 or higher, a trench is not fully filled with such anoxide layer. As an alternative, use of a layer of SOG (spin on glass)was proposed. Since the SOG is originally liquid or sol-phase, it hasexcellent gap-fill characteristics to reduce a step difference.Generally, the SOG is coated on a semiconductor substrate.

As an example, hydro silsesquioxane (HSQ) is an example of a SOG, andgenerally a liquid-phase HSQ layer is coated on a substrate. The coatedHSQ layer is first heated using a low temperature (100° C. to 300° C. ),i.e., soft-baked, to remove any solvent ingredients such as dialkylether. The HSQ layer coating is then heated at a high temperature (400°C. ), i.e., hard-baked, for over 10 minutes to harden the HSQ layercoating.

Even if the HSQ layer is subject to a hard-bake process in an oxygenambient, it is scarcely cured. In this case, “cured” means that anelement, except oxygen and silicon, is replaced with oxygen to formsilicon oxide. When the SOG layer is used to fill a narrow-and-deep voidbetween patterns, it is hard to diffuse oxygen and an oxygen-combinedingredient. Curing occurs at the top surface of the SOG layer, andconsequently, the cured top surface portion of the SOG layer preventsoxygen from diffusing into the HSQ layer. Consequently, crystallizationof the HSQ layer into a silicon oxide layer occurs slowly. If the HSQlayer is poorly cured, hydrogen remains in the HSQ SOG layer and causesthe formation of a porous layer. When this porous layer is subject to awet etch, the amount of porous layer that is etched over time increasesrapidly leading to instability, unreliability and unpredictability inthe etching or cleaning process.

A volume shrinkage may also occur while processing the coated HSQ layer,and this may cause the formation of cracks and fissures in a subsequentannealing process. Compared with a well-cured portion, a stressdifference occurs during thermal expansion. This leads to the creationof cracks and therefore a lowering of the reliability of the device. Asa result, the HSQ layer is not desirable as a composition layer.

In an effort to overcome the foregoing disadvantages, it has beenproposed to form a layer of LPCVD TEOS in a trench that is partiallyfilled with HSQ, see “Shallow Trench Isolation Fill for 1 Gbit DRAM andBeyond Using a Hydrogen Silsesquioxane Glass/LPCVD TEOS HybridApproach,” contributed to the DUMIC Conference by IBM, 1998.Unfortunately, such an approach requires a separate processing becausethe conformality of the coating is reduced. If filling a trench with HSQis beyond a reasonable degree, defects are possibly formed in subsequentprocess steps.

A method of filling a lower portion of a trench with SOG is disclosed inJapanese Patent Publication No. 2000-183150. First, an organicingredient is used as SOG to fill a trench for device isolation. In thiscase, the effects of an oxygen plasma process are not sufficientlytransferred to a lower portion of the SOG. This occurs because aplasma-treated upper portion of the SOG is easily etched while a lowerportion of the SOG is not or at least insignificantly etched. Thus, theSOG remains at the lower portion of the trench. A remaining portion ofthe trench is filled with an oxide such as HDP CVD. Such a process isused to fill a trench of a high aspect ratio with an oxide withoutcreating voids or seams. Unfortunately, remaining organic ingredients,such as carbon, have an adverse effect on the insulation of a deviceisolation layer.

In this regard, the present invention provides a method of forming atrench-type device isolation layer in a trench of a high aspect ratiowithout the drawbacks and disadvantages of the prior art as described.The present invention also provides a method of forming a trench-typedevice isolation layer, which can increase a processing margin andenhance characteristics and reliability of products, using spin on glass(SOG) technology.

SUMMARY OF THE INVENTION

According to a preferred embodiment of the present invention,polysilazane is coated on a substrate, in which a trench for deviceisolation is formed, using a spin on glass (SOG) technique. Using theSOG coating step, the thickness of the coating may be controlled so asto fill only a predetermined portion of the trench with SOG. However, itis preferable that the trench is almost entirely filled with SOG, andthen the SOG is etched to a predetermined depth thereby exposing a topportion of the trench. This results in an enhancement of theconformality of the SOG coating.

Preferably, a thin solution containing between about 5 to about 20%polysilizane (a solid-state material decreases in content) is used tomaintain a conformal coating thickness without overfilling the trench.More preferably, a polysilazane solution containing between about 5 toabout 15 percent by weight, perhydro-polysilazane ([SiH₂NH]n), which maybe easily annealed at a high temperature, is used.

After formation of the SOG layer, a subsequent process is carried out toturn the SOG layer into a silicon oxide layer of silicon dioxidestructure. This subsequent process is divided into two steps, baking andannealing. In the baking step, a solvent in the solution is removed. Inthe annealing step, an organic ingredient or nitrogen and hydrogeningredients of the polysilazane are replaced with oxygen to initiate theformation of a silicon oxide layer. Preferably, the annealing step isperformed prior to a recess step in which the SOG layer is etched toexpose a top portion of the trench. Alternatively, the annealing stepmay be performed subsequent to the recess step. Preferably, the SOGlayer is etched down a thickness of 1000 Å from a top surface of thesilicon substrate.

Using a CVD technique, a silicon oxide layer is stacked on a remainingSOG layer in which a trench is partially filled. The CVD oxide layer ispreferably made of ozone TEOS USG or HDP CVD having good gap-fillproperties. After formation of the silicon oxide layer, a planarizationstep is further carried out using a CMP technique so as to complete adevice isolation layer.

These and other features and aspects of the present invention will bereadily apparent to those of ordinary skill in the art upon review ofthe detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will becomemore apparent by describing in detail a preferred embodiment thereofwith reference to the attached drawings in which:

FIG. 1 through FIG. 5 illustrate cross-sectional views of the processingsteps of forming a trench-type device isolation layer in accordance withan embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Korean Patent Application No. 2001-11142, filed on Mar. 5, 2001, andentitled: “Method of Forming Insulating Layer in Trench Isolation TypeSemiconductor Device,” is incorporated herein by reference in itsentirety.

The present invention now will be described more fully with reference tothe accompanying drawings, in which preferred embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the concept of the invention to those skilled in the art.

Referring to FIG. 1, a silicon nitride layer (not indicated) is stackedon a semiconductor substrate 10 on which a pad oxide layer 11 is formed.Using a photoresist (not shown), the silicon nitride layer is patternedto form a trench etch mask pattern 13 through exposure and etch steps.Using the trench etch mask pattern 13, the substrate 10 isanisotropically etched to form a trench 19 for device isolation. Athermal oxide layer 15 is formed on an inner wall of the trench to cureany crystalline defects. A silicon nitride liner 17 is formed on thethermal oxide layer to a thickness of about 100 Å or less.

Referring now to FIG. 2, a polysilazane solution is coated on asubstrate 10 by a spin on glass (SOG) manner in order to fill a trench.Among the SOG materials, a silazane group ([SiR1R2NR3]n) generally hasan average molecular weight between about 1000 to 10,000. Also, thesilazane group is perhydro polysilazane in which all the R1, R2, and R3are hydrogen or is organic polysilazane in which each of the R1, R2, andR3 is an organic atomic group such as alkyl group, aryl group, or alkoxygroup. The polysilazane of a constant percent by weight is included inan organic solution such as dibuthyl ether, toluene, and xylene for useas a coating. Such an SOG coating material, conventionally calledpolysilazane, can be annealed at a relatively lower temperature than asiloxane group, including silicate or silsesquioxane. Therefore, a morecomplete curing is achieved in order to enhance resistivity to a wetetch. Moreover, such a polysilazane is more easily applied to a processthan is HSQ.

The thickness of the SOG layer 21 is determined and controlled by twofactors: a solid percent by weight of the polysilazane solution and thespeed of a spinner used in coating. When using a low content andviscosity solid (e.g., a solution having a solid content of about 12% indibuthyl ether), an SOG layer can be formed to fill the most concaveportion of a trench with the solution. Also, the SOG layer can beformed, having a low thickness, at a convex portion that is an activeregion covered with a silicon nitride mask. A thin polysilazane solutionis advantageous in achieving a good step coverage. However, if thepolysilazane solution is too thin, it is difficult to control thethickness of a layer and also form the SOG layer at one time.

In a preferred embodiment, a coating condition of the polysilazane isthat a concentration of the polysilazane is 5 to 15 percent by weightand the spinner is rounded at 1000 to 5000 rpm (revolutions per minute).A trench having a depth of 5000 Å and a width of 1000 Å is filled withthe SOG layer 21 at a substantially irregularly-shaped zone in a narrowpart of a cell area. A very thin SOG layer (e.g., 500 Å or less,preferably less than 100 Å) is formed at the active region that iscovered with an etch mask pattern of a silicon nitride layer. However,the SOG layer is conformally formed in a peripheral circuit area inwhich a trench or an active region is widely formed. In this case, theSOG layer is gently inclined at an interface.

In coating the polysilazane, a solvent ingredient is removed through abake process that is one of a pre-bake process (between about 80° C. to350° C. ), a hard-bake process (approximately 400° C.), or a combinationof these processes. In this embodiment, the pre-bake process is carriedout for several minutes to remove most of the solvent ingredient.Thereafter, the hard-bake process is carried out to heat a semiconductorsubstrate at a temperature of 400° C. to 450° C. for 30 minutes. Thehard-bake process is carried out in an inert gas, such as nitrogen, or avacuum ambient. By this procedure, a solvent ingredient and a gas-phaseingredient containing silane gas, nitrogen, and hydrogen issue from theSOG layer.

An annealing process is carried out at a temperature of between about700° C. to about 800° C. in a steam-supplied oxidation ambient for aboutan hour, which is called “curing,” to form a silicon oxide layer. Inthis case, silicon-excluded ingredients, for example, organicingredients, are removed from the polysilazane, and oxygen is introducedto form the silicon oxide layer. Also, the annealing process ispreferably carried out in a nitrogen ambient or in an air ambientincluding oxygen and steam.

Referring now to FIG. 3, the cured SOG layer 211 is etched to remove atop portion thereof. That is, the cured SOG layer 211 is etched so thatthe top of the cured SOG layer 211 is recessed below the level of a topsurface of the semiconductor substrate. The recess is made to a similarthickness with respect to the entire substrate, making it significant touniformly coat the SOG layer 211 over the entire substrate. Preferably,the SOG layer 211 is thin and an upper portion of the SOG layer 211 isetched to about 1000 Å from a top surface of the silicon substrate. Inthis regard, an etch-back technique using a wet or dry etchant is moresuitable to the recessing procedure than a chemical mechanical polishing(CMP) technique. A slight recess is advantageous to gap-fill in asubsequent process for filling an oxide layer. Nevertheless, a degree ofthe recess must be determined considering the fact that the SOG layer211 is exposed in the following process and is easily attacked under thetrench of a high etch rate in an etch or a cleaning process.

Under the premise that the curing is normally made, an upper portion ofthe SOG layer is changed to a silicon oxide layer while the SOG layer ina deeper part of the trench is oxidized more restrictively. Therefore,an etch rate is easily controllable in recessing an SOG layer from thetop surface of the silicon substrate by 1000 Å. For example, using a LAL2000 solution that contains hydrofluoric acid and ammonium hydroxide,which etches a thermal oxide layer at a rate of about 200 Å/minute, theSOG layer is etched at a rate of about 600 Å/minute. This result ishigher than that of the thermal oxide layer but is controllable incomparison with the conventional HSQ SOG layer.

Referring now to FIG. 4, a silicon oxide layer 31 is deposited on asubstrate in which an SOG layer 211 is recessed in a trench. Thedeposition of the silicon oxide layer 31 is made by, for example, theHDP CVD manner of a high gap-fill capability. In this case, a depositionthickness is sufficient to cover the entire substrate. Conventionally, aprocess of densifying the CVD silicon oxide layer is subsequent. By theCMP technique, however, the CVD silicon oxide layer is planarized toexpose the trench etch mask pattern 13.

Referring now to FIG. 5, a silicon nitride layer used as a trench etchmask pattern 13 and a pad oxide layer 11 are removed to complete atrench-type device isolation layer that is composed of a lower SOG layer211 and an upper silicon oxide layer 311. Preferably, the deviceisolation layer filling the trench is partially etched to be level withthe substrate.

A preferred embodiment of the present invention has been disclosedherein and, although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

What is claimed is:
 1. A method of forming a trench-type deviceisolation layer, comprising: coating a polysilazane solution on asemiconductor substrate in a spin on glass (SOG) manner to form an SOGlayer filling a trench formed in the semiconductor substrate for deviceisolation; performing a thermal process for changing an upper portion ofthe SOG layer to a silicon oxide layer; etching the thermally treatedSOG layer to form a remaining SOG layer filling a predetermined portionof the trench, such that a top surface of the remaining SOG layer isrecessed from a top surface of the semiconductor substrate by about 1000Å; and stacking a CVD type silicon oxide layer on the remaining SOGlayer to fill a remaining portion of the trench.
 2. A method of forminga trench-type device isolation layer, comprising: coating a polysilazanesolution on a semiconductor substrate in a spin on glass (SOG) manner toform an SOG layer filling a trench formed in the semiconductor substratefor device isolation, wherein a solid ingredient of the polysilazanesolution is between about 5 to about 20 percent by weight and the SOGlayer is coated on an active region around the trench to a thickness ofabout 500 Å or less; performing a thermal process for changing an upperportion of the SOG layer to a silicon oxide layer; etching the thermallytreated SOG layer to form a remaining SOG layer filling a predeterminedportion of the trench; and stacking a CVD type silicon oxide layer onthe remaining SOG layer to fill a remaining portion of the trench. 3.The method as claimed in claim 2, wherein the subsequent thermal processconsists of a bake process and an annealing process that is performed ina steam (H₂O)-supplied oxidation ambient at a temperature of betweenabout 700° C. to about 800° C. for between about 10 to about 60 minutes.4. The method as claimed in claim 2, wherein the polysilazane solutioncontains only a solid-state perhydro polysilazane ([SiH₂NH]n) of betweenabout 5 to about 15 percent by weight.
 5. The method as claimed in claim2, wherein the CVD type silicon oxide layer is formed using a highdensity plasma (HDP) CVD.
 6. The method as claimed in claim 5, furthercomprising planarizing the silicon oxide layer in a chemical mechanicalpolishing (CMP) manner after the formation thereof.
 7. The method asclaimed in claim 2, wherein the thermal process includes a bake processand an annealing process that is performed in a steam (H₂O) and anitrogen (N₂)-supplied oxidation ambient at a temperature of betweenabout 700° C. to about 800° C. for between about 10 to about 60 minutes.8. A method of forming a trench-type device isolation layer, comprising:stacking a pad oxide layer on a silicon substrate; stacking a siliconnitride layer on the pad oxide layer; patterning the silicon nitridelayer to form a trench etch mask pattern; etching the pad oxide layerand the substrate to form a trench for device isolation; forming athermal oxide layer on an inner wall of the trench such that the thermaloxide layer covers a bottom and sidewalls of the trench to a level thatis even with the silicon nitride layer so that the trench has a convexportion that is an active region at the sidewall of the trench where thepad oxide layer meets the silicon nitride layer; forming a siliconnitride liner on the entire substrate including the thermal oxide layer;coating a polysilazane solution on the semiconductor substrate in a spinon glass (SOG) manner to form an SOG layer filling the trench formed inthe semiconductor substrate for device isolation, wherein a solidingredient of the polysilazane solution is between about 5 to about 20percent by weight and the SOG layer is coated on the convex portion ofthe trench that is an active region to a thickness of about 500 Å orless; performing a thermal process for changing an upper portion of theSOG layer to a silicon oxide layer; etching the thermally treated SOGlayer to form a remaining SOG layer filling a predetermined portion ofthe trench; stacking a CVD type silicon oxide layer on the remaining SOGlayer to fill a remaining portion of the trench; and removing thesilicon nitride layer and pad oxide layer.
 9. The method as claimed inclaim 8, wherein the subsequent thermal process consists of a bakeprocess and an annealing process that is performed in a steam(H₂O)-supplied oxidation ambient at a temperature of between about 700°C. to about 800° C. for between about 10 to about 60 minutes.
 10. Themethod as claimed in claim 8, wherein the SOG layer is etched to make atop surface of the remaining SOG layer recessed from a top surface ofthe semiconductor substrate by about 1000 Å.
 11. The method as claimedin claim 8, wherein the polysilazane solution contains only asolid-state perhydro polysilazane ([SiH₂NH]n) of between about 5 toabout 15 percent by weight.
 12. The method as claimed in claim 8,wherein the CVD type silicon oxide layer is formed using a high densityplasma (HDP) CVD.
 13. The method as claimed in claim 12, furthercomprising planarizing the silicon oxide layer in a chemical mechanicalpolishing (CMP) manner after the formation thereof.
 14. The method asclaimed in claim 8, wherein the subsequent process includes a bakeprocess and an annealing process that is performed in a steam (H₂O) anda nitrogen (N₂)-supplied oxidation ambient at a temperature of betweenabout 700° C. to about 800° C. for between about 10 to about 60 minutes.